ESD Testing

From Components to Systems
 
 
John Wiley & Sons Inc (Verlag)
  • erschienen am 7. Oktober 2016
  • |
  • 328 Seiten
 
E-Book | PDF mit Adobe DRM | Systemvoraussetzungen
978-1-118-70714-2 (ISBN)
 
With the evolution of semiconductor technology and global diversification of the semiconductor business, testing of semiconductor devices to systems for electrostatic discharge (ESD) and electrical overstress (EOS) has increased in importance.
ESD Testing: From Components to Systems updates the reader in the new tests, test models, and techniques in the characterization of semiconductor components for ESD, EOS, and latchup.
Key features:
* Provides understanding and knowledge of ESD models and specifications including human body model (HBM), machine model (MM), charged device model (CDM), charged board model (CBM), cable discharge events (CDE), human metal model (HMM), IEC 61000-4-2 and IEC 61000-4-5.
* Discusses new testing methodologies such as transmission line pulse (TLP), to very fast transmission line pulse (VF-TLP), and future methods of long pulse TLP, to ultra-fast TLP (UF-TLP).
* Describes both conventional testing and new testing techniques for both chip and system level evaluation.
* Addresses EOS testing, electromagnetic compatibility (EMC) scanning, to current reconstruction methods.
* Discusses latchup characterization and testing methodologies for evaluation of semiconductor technology to product testing.
ESD Testing: From Components to Systems is part of the authors' series of books on electrostatic discharge (ESD) protection; this book will be an invaluable reference for the professional semiconductor chip and system-level ESD and EOS test engineer. Semiconductor device and process development, circuit designers, quality, reliability and failure analysis engineers will also find it an essential reference. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, semiconductor testing and experimental work.
weitere Ausgaben werden ermittelt
Dr Steven H. Voldman, IEEE Fellow, Vermont, USA
Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for "Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology." Voldman was a member of the semiconductor development of IBM for 25 years as well as a consultant for TSMC, and Samsung Electronics. Dr. Voldman initiated the first transmission line pulse (TLP) standard development team, and a participant in the JEDEC-ESD Association standards harmonization of the human body model (HBM) Standard. From 2000 to 2013, as Chairman of the ESD Association Work Group on TLP and very-fast TLP (VF-TLP), his team was responsible for initiating the first standard practice and standards for TLP and VF-TLP.He initiated the "ESD on Campus" program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 40 universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, and China. Dr. Voldman teaches short courses and tutorials on ESD, latchup, patenting, and invention.
1 - Cover [Seite 1]
2 - Title Page [Seite 5]
3 - Copyright [Seite 6]
4 - Dedication [Seite 7]
5 - Contents [Seite 9]
6 - About the Author [Seite 19]
7 - Preface [Seite 21]
8 - Acknowledgments [Seite 25]
9 - Chapter 1 Introduction [Seite 27]
9.1 - 1.1 Testing for ESD, EMI, EOS, EMC, and Latchup [Seite 27]
9.2 - 1.2 Component and System Level Testing [Seite 27]
9.3 - 1.3 Qualification Testing [Seite 28]
9.4 - 1.4 ESD Standards [Seite 29]
9.4.1 - 1.4.1 Standard Development-Standard Practice (SP) and Standard Test Methods (STMs) [Seite 29]
9.4.2 - 1.4.2 Repeatability [Seite 30]
9.4.3 - 1.4.3 Reproducibility [Seite 30]
9.4.4 - 1.4.4 Round Robin Testing [Seite 30]
9.4.5 - 1.4.5 Round Robin Statistical Analysis-k-Statistics [Seite 31]
9.4.6 - 1.4.6 Round Robin Statistical Analysis-h-Statistics [Seite 32]
9.5 - 1.5 Component Level Standards [Seite 32]
9.6 - 1.6 System Level Standards [Seite 33]
9.7 - 1.7 Factory and Material Standards [Seite 33]
9.8 - 1.8 Characterization Testing [Seite 34]
9.8.1 - 1.8.1 Semiconductor Component Level Characterization [Seite 35]
9.8.2 - 1.8.2 Semiconductor Device Level Characterization [Seite 35]
9.8.3 - 1.8.3 Wafer Level ESD Characterization Testing [Seite 35]
9.8.4 - 1.8.4 Device Characterization Tests on Circuits [Seite 36]
9.8.5 - 1.8.5 Device Characterization Tests on Components [Seite 36]
9.8.6 - 1.8.6 System level Characterization on Components [Seite 37]
9.8.7 - 1.8.7 Testing to Standard Specification Levels [Seite 37]
9.8.8 - 1.8.8 Testing to Failure [Seite 37]
9.9 - 1.9 ESD Library Characterization and Qualification [Seite 38]
9.10 - 1.10 ESD Component Standards and Chip Architectures [Seite 38]
9.10.1 - 1.10.1 Relationship Between ESD Standard Pin Combinations and Failure Mechanisms [Seite 38]
9.10.2 - 1.10.2 Relationship Between ESD Standard Pin Combinations and Chip Architecture [Seite 39]
9.11 - 1.11 System Level Characterization [Seite 39]
9.12 - 1.12 Summary and Closing Comments [Seite 39]
9.13 - Problems [Seite 40]
9.14 - References [Seite 41]
10 - Chapter 2 Human Body Model [Seite 43]
10.1 - 2.1 History [Seite 43]
10.2 - 2.2 Scope [Seite 44]
10.3 - 2.3 Purpose [Seite 44]
10.4 - 2.4 Pulse Waveform [Seite 44]
10.5 - 2.5 Equivalent Circuit [Seite 45]
10.6 - 2.6 Test Equipment [Seite 46]
10.7 - 2.7 Test Sequence and Procedure [Seite 49]
10.8 - 2.8 Failure Mechanisms [Seite 51]
10.9 - 2.9 HBM ESD Current Paths [Seite 52]
10.10 - 2.10 HBM ESD Protection Circuit Solutions [Seite 54]
10.11 - 2.11 Alternate Test Methods [Seite 58]
10.11.1 - 2.11.1 HBM Split Fixture Testing [Seite 58]
10.11.2 - 2.11.2 HBM Sample Testing [Seite 59]
10.11.3 - 2.11.3 HBM Wafer Level ESD Testing [Seite 59]
10.11.4 - 2.11.4 HBM Test Extraction Across the Device Under Test (DUT) [Seite 59]
10.12 - 2.12 HBM Two-Pin Stress [Seite 60]
10.12.1 - 2.12.1 HBM Two-Pin Stress-Advantages [Seite 63]
10.12.2 - 2.12.2 HBM Two-Pin Stress-Pin Combinations [Seite 63]
10.13 - 2.13 HBM Small Step Stress [Seite 63]
10.13.1 - 2.13.1 HBM Small Step Stress-Advantages [Seite 64]
10.13.2 - 2.13.2 HBM Small Step Stress-Data Analysis Methods [Seite 64]
10.13.3 - 2.13.3 HBM Small Step Stress-Design Optimization [Seite 64]
10.14 - 2.14 Summary and Closing Comments [Seite 64]
10.15 - Problems [Seite 65]
10.16 - References [Seite 65]
11 - Chapter 3 Machine Model [Seite 69]
11.1 - 3.1 History [Seite 69]
11.2 - 3.2 Scope [Seite 69]
11.3 - 3.3 Purpose [Seite 69]
11.4 - 3.4 Pulse Waveform [Seite 70]
11.4.1 - 3.4.1 Comparison of Machine Model (MM) and Human Body Model (HBM) Pulse Waveform [Seite 70]
11.5 - 3.5 Equivalent Circuit [Seite 71]
11.6 - 3.6 Test Equipment [Seite 71]
11.7 - 3.7 Test Sequence and Procedure [Seite 73]
11.8 - 3.8 Failure Mechanisms [Seite 75]
11.9 - 3.9 MM ESD Current Paths [Seite 75]
11.10 - 3.10 MM ESD Protection Circuit Solutions [Seite 78]
11.11 - 3.11 Alternate Test Methods [Seite 81]
11.11.1 - 3.11.1 Small Charge Model (SCM) [Seite 81]
11.12 - 3.12 Machine Model to Human Body Model Ratio [Seite 83]
11.13 - 3.13 Machine Model Status as an ESD Standard [Seite 84]
11.14 - 3.14 Summary and Closing Comments [Seite 84]
11.15 - Problems [Seite 85]
11.16 - References [Seite 85]
12 - Chapter 4 Charged Device Model (CDM) [Seite 87]
12.1 - 4.1 History [Seite 87]
12.2 - 4.2 Scope [Seite 87]
12.3 - 4.3 Purpose [Seite 88]
12.4 - 4.4 Pulse Waveform [Seite 88]
12.4.1 - 4.4.1 Charged Device Model Pulse Waveform [Seite 88]
12.4.2 - 4.4.2 Comparison of Charged Device Model (CDM) and Human Body Model (HBM) Pulse Waveform [Seite 89]
12.5 - 4.5 Equivalent Circuit [Seite 91]
12.6 - 4.6 Test Equipment [Seite 91]
12.7 - 4.7 Test Sequence and Procedure [Seite 93]
12.8 - 4.8 Failure Mechanisms [Seite 95]
12.9 - 4.9 CDM ESD Current Paths [Seite 96]
12.10 - 4.10 CDM ESD Protection Circuit Solutions [Seite 98]
12.11 - 4.11 Alternative Test Methods [Seite 100]
12.11.1 - 4.11.1 Alternative Test Methods-Socketed Device Model (SDM) [Seite 100]
12.12 - 4.12 Charged Board Model (CBM) [Seite 101]
12.12.1 - 4.12.1 Comparison of Charged Board Model (CBM) and Charged Device Model (CDM) Pulse Waveform [Seite 101]
12.12.2 - 4.12.2 Charged Board Model (CBM) as an ESD Standard [Seite 103]
12.13 - 4.13 Summary and Closing Comments [Seite 103]
12.14 - Problems [Seite 105]
12.15 - References [Seite 106]
13 - Chapter 5 Transmission Line Pulse (TLP) Testing [Seite 110]
13.1 - 5.1 History [Seite 110]
13.2 - 5.2 Scope [Seite 111]
13.3 - 5.3 Purpose [Seite 111]
13.4 - 5.4 Pulse Waveform [Seite 112]
13.5 - 5.5 Equivalent Circuit [Seite 113]
13.6 - 5.6 Test Equipment [Seite 114]
13.6.1 - 5.6.1 Current Source [Seite 116]
13.6.2 - 5.6.2 Time Domain Reflection (TDR) [Seite 116]
13.6.3 - 5.6.3 Time Domain Transmission (TDT) [Seite 117]
13.6.4 - 5.6.4 Time Domain Reflection and Transmission (TDRT) [Seite 117]
13.6.5 - 5.6.5 Commercial Transmission Line Pulse (TLP) Systems [Seite 118]
13.7 - 5.7 Test Sequence and Procedure [Seite 121]
13.7.1 - 5.7.1 TLP Pulse Analysis [Seite 122]
13.7.2 - 5.7.2 Measurement Window [Seite 122]
13.7.3 - 5.7.3 Measurement Analysis-TDR Voltage Waveform [Seite 122]
13.7.4 - 5.7.4 Measurement Analysis-Time Domain Reflection (TDR) Current Waveform [Seite 123]
13.7.5 - 5.7.5 Measurement Analysis-Time Domain Reflection (TDR) Current-Voltage Characteristic [Seite 124]
13.8 - 5.8 TLP Pulsed I-V Characteristic [Seite 124]
13.8.1 - 5.8.1 TLP I-V Characteristic Key Parameters [Seite 125]
13.8.2 - 5.8.2 TLP Power Versus Time [Seite 125]
13.8.3 - 5.8.3 TLP Power Versus Time-Measurement Analysis [Seite 126]
13.8.4 - 5.8.4 TLP Power-to-Failure Versus Pulse Width Plot [Seite 126]
13.9 - 5.9 Alternate Methods [Seite 127]
13.9.1 - 5.9.1 Long Duration TLP (LD-TLP) [Seite 127]
13.9.2 - 5.9.2 Long Duration TLP Time Domain [Seite 128]
13.10 - 5.10 TLP-to-HBM Ratio [Seite 130]
13.10.1 - 5.10.1 Comparison of Transmission Line Pulse (TLP) and Human Body Model (HBM) Pulse Width [Seite 130]
13.11 - 5.11 Summary and Closing Comments [Seite 130]
13.12 - Problems [Seite 130]
13.13 - References [Seite 131]
14 - Chapter 6 Very Fast Transmission Line Pulse (VF-TLP) Testing [Seite 134]
14.1 - 6.1 History [Seite 134]
14.2 - 6.2 Scope [Seite 134]
14.3 - 6.3 Purpose [Seite 134]
14.4 - 6.4 Pulse Waveform [Seite 135]
14.4.1 - 6.4.1 Comparison of VF-TLP Versus TLP Waveform [Seite 136]
14.5 - 6.5 Equivalent Circuit [Seite 137]
14.6 - 6.6 Test Equipment Configuration [Seite 137]
14.6.1 - 6.6.1 Current Source [Seite 138]
14.6.2 - 6.6.2 Time Domain Reflection (TDR) [Seite 138]
14.6.3 - 6.6.3 Time Domain Transmission (TDT) [Seite 138]
14.6.4 - 6.6.4 Time Domain Reflection and Transmission (TDRT) [Seite 139]
14.6.5 - 6.6.5 Early VF-TLP Systems [Seite 140]
14.6.6 - 6.6.6 Commercial VF-TLP Test Systems [Seite 142]
14.7 - 6.7 Test Sequence and Procedure [Seite 143]
14.7.1 - 6.7.1 VF-TLP Pulse Analysis [Seite 144]
14.7.2 - 6.7.2 Measurement Window [Seite 144]
14.7.3 - 6.7.3 Measurement Analysis-VF-TLP Voltage Waveform [Seite 144]
14.7.4 - 6.7.4 Measurement Analysis-Time Domain Reflectometry (TDR) Current Waveform [Seite 144]
14.7.5 - 6.7.5 Measurement Analysis-Time Domain Transmission (TDR) Current-Voltage Characteristics [Seite 145]
14.8 - 6.8 VF-TLP Pulsed I-V Characteristics [Seite 147]
14.8.1 - 6.8.1 VF-TLP Pulsed I-V Characteristic Key Parameters [Seite 147]
14.8.2 - 6.8.2 VF-TLP Power Versus Time Plot [Seite 148]
14.8.3 - 6.8.3 VF-TLP Power Versus Time-Measurement Analysis [Seite 149]
14.8.4 - 6.8.4 VF-TLP Power-to-Failure Versus Pulse Width Plot [Seite 149]
14.8.5 - 6.8.5 VF-TLP and TLP Power-to-Failure Plot [Seite 150]
14.9 - 6.9 Alternate Test Methods [Seite 150]
14.9.1 - 6.9.1 Radio Frequency (RF) VF-TLP Systems [Seite 150]
14.9.2 - 6.9.2 Ultrafast Transmission Line Pulse (UF-TLP) [Seite 151]
14.10 - 6.10 Summary and Closing Comments [Seite 151]
14.11 - Problems [Seite 154]
14.12 - References [Seite 154]
15 - Chapter 7 IEC 61000-4-2 [Seite 156]
15.1 - 7.1 History [Seite 156]
15.2 - 7.2 Scope [Seite 156]
15.3 - 7.3 Purpose [Seite 156]
15.3.1 - 7.3.1 Air Discharge [Seite 157]
15.3.2 - 7.3.2 Direct Contact Discharge [Seite 157]
15.4 - 7.4 Pulse Waveform [Seite 157]
15.4.1 - 7.4.1 Pulse Waveform Equation [Seite 158]
15.5 - 7.5 Equivalent Circuit [Seite 159]
15.6 - 7.6 Test Equipment [Seite 159]
15.6.1 - 7.6.1 Test Configuration [Seite 160]
15.6.2 - 7.6.2 ESD Guns [Seite 160]
15.6.3 - 7.6.3 ESD Guns-Standard Versus Discharge Module [Seite 161]
15.6.4 - 7.6.4 Human Body Model Versus IEC 61000-4-2 [Seite 161]
15.7 - 7.7 Test Sequence and Procedure [Seite 161]
15.8 - 7.8 Failure Mechanisms [Seite 163]
15.9 - 7.9 IEC 61000-4-2 ESD Current Paths [Seite 164]
15.10 - 7.10 ESD Protection Circuitry Solutions [Seite 165]
15.11 - 7.11 Alternative Test Methods [Seite 166]
15.11.1 - 7.11.1 Automotive ESD Standards [Seite 167]
15.11.2 - 7.11.2 Medical ESD Standards [Seite 168]
15.11.3 - 7.11.3 Avionic ESD Standard [Seite 169]
15.11.4 - 7.11.4 Military-Related ESD Standard [Seite 169]
15.12 - 7.12 Summary and Closing Comments [Seite 169]
15.13 - Problems [Seite 169]
15.14 - References [Seite 170]
16 - Chapter 8 Human Metal Model (HMM) [Seite 173]
16.1 - 8.1 History [Seite 173]
16.2 - 8.2 Scope [Seite 173]
16.3 - 8.3 Purpose [Seite 174]
16.4 - 8.4 Pulse Waveform [Seite 174]
16.4.1 - 8.4.1 Pulse Waveform Equation [Seite 174]
16.5 - 8.5 Equivalent Circuit [Seite 175]
16.6 - 8.6 Test Equipment [Seite 175]
16.7 - 8.7 Test Configuration [Seite 176]
16.7.1 - 8.7.1 Horizontal Configuration [Seite 177]
16.7.2 - 8.7.2 Vertical Configuration [Seite 177]
16.7.3 - 8.7.3 HMM Fixture Board [Seite 178]
16.8 - 8.8 Test Sequence and Procedure [Seite 179]
16.8.1 - 8.8.1 Current Waveform Verification [Seite 180]
16.8.2 - 8.8.2 Current Probe Verification Methodology [Seite 180]
16.8.3 - 8.8.3 Current Probe Waveform Comparison [Seite 182]
16.9 - 8.9 Failure Mechanisms [Seite 183]
16.10 - 8.10 ESD Current Paths [Seite 184]
16.11 - 8.11 ESD Protection Circuit Solutions [Seite 184]
16.12 - 8.12 Summary and Closing Comments [Seite 186]
16.13 - Problems [Seite 186]
16.14 - References [Seite 187]
17 - Chapter 9 IEC 61000-4-5 [Seite 189]
17.1 - 9.1 History [Seite 189]
17.2 - 9.2 Scope [Seite 190]
17.3 - 9.3 Purpose [Seite 190]
17.4 - 9.4 Pulse Waveform [Seite 191]
17.5 - 9.5 Equivalent Circuit [Seite 192]
17.6 - 9.6 Test Equipment [Seite 192]
17.7 - 9.7 Test Sequence and Procedure [Seite 194]
17.8 - 9.8 Failure Mechanisms [Seite 194]
17.9 - 9.9 IEC 61000-4-5 ESD Current Paths [Seite 196]
17.10 - 9.10 ESD Protection Circuit Solutions [Seite 196]
17.11 - 9.11 Alternate Test Methods [Seite 197]
17.12 - 9.12 Summary and Closing Comments [Seite 197]
17.13 - Problems [Seite 198]
17.14 - References [Seite 198]
18 - Chapter 10 Cable Discharge Event (CDE) [Seite 200]
18.1 - 10.1 History [Seite 200]
18.2 - 10.2 Scope [Seite 201]
18.3 - 10.3 Purpose [Seite 201]
18.4 - 10.4 Cable Discharge Event-Charging, Discharging, and Pulse Waveform [Seite 201]
18.4.1 - 10.4.1 Charging Process [Seite 202]
18.4.2 - 10.4.2 Discharging Process [Seite 202]
18.4.3 - 10.4.3 Pulse Waveform [Seite 202]
18.4.4 - 10.4.4 Comparison of CDE and IEC 61000-4-2 Pulse Waveform [Seite 202]
18.5 - 10.5 Equivalent Circuit [Seite 204]
18.6 - 10.6 Test Equipment [Seite 205]
18.6.1 - 10.6.1 Commercial Test Systems [Seite 205]
18.7 - 10.7 Test Measurement [Seite 206]
18.7.1 - 10.7.1 Measurement [Seite 206]
18.7.2 - 10.7.2 Measurement -Transmission Line Test Generators [Seite 206]
18.7.3 - 10.7.3 Measurement-Low-Impedance Transmission Line Waveform [Seite 207]
18.7.4 - 10.7.4 Schematic Capturing System Response to Reference Waveform [Seite 208]
18.7.5 - 10.7.5 Tapered Transmission Lines [Seite 211]
18.7.6 - 10.7.6 ESD Current Sensor [Seite 211]
18.8 - 10.8 Test Procedure [Seite 211]
18.9 - 10.9 Measurement of a Cable in Different Conditions [Seite 211]
18.9.1 - 10.9.1 Test System Configuration and Diagram [Seite 213]
18.9.2 - 10.9.2 Cable Configurations-Handheld Cable [Seite 215]
18.9.3 - 10.9.3 Cable Configuration-Taped to Ground Plane [Seite 217]
18.9.4 - 10.9.4 Cable Configurations-Pulse Analysis Summary [Seite 217]
18.10 - 10.10 Transient Field Measurements [Seite 221]
18.10.1 - 10.10.1 Transient Field Measurement of Short-Length Cable Discharge Events [Seite 221]
18.10.2 - 10.10.2 Antenna-Induced Voltages [Seite 221]
18.11 - 10.11 Telecommunication Cable Discharge Test System [Seite 221]
18.12 - 10.12 Cable Discharge Current Paths [Seite 226]
18.13 - 10.13 Failure Mechanisms [Seite 226]
18.13.1 - 10.13.1 Cable Discharge Event Failure-Connector Failure [Seite 226]
18.13.2 - 10.13.2 Cable Discharge Event Failure-Printed Circuit Board [Seite 227]
18.13.3 - 10.13.3 Cable Discharge Event Failure-Semiconductor On-Chip [Seite 227]
18.13.4 - 10.13.4 Cable Discharge Event (CDE)-Induced Latchup [Seite 227]
18.14 - 10.14 Cable Discharge Event (CDE) Protection [Seite 227]
18.14.1 - 10.14.1 RJ-45 Connectors [Seite 228]
18.14.2 - 10.14.2 Printed Circuit Board Design Considerations [Seite 228]
18.14.3 - 10.14.3 ESD Circuitry [Seite 228]
18.14.4 - 10.14.4 Cable Discharge Event (CDE) ESD Protection Validation [Seite 229]
18.15 - 10.15 Alternative Test Methods [Seite 229]
18.16 - 10.16 Summary and Closing Comments [Seite 230]
18.17 - Problems [Seite 230]
18.18 - References [Seite 230]
19 - Chapter 11 Latchup [Seite 232]
19.1 - 11.1 History [Seite 232]
19.2 - 11.2 Purpose [Seite 234]
19.3 - 11.3 Scope [Seite 235]
19.4 - 11.4 Pulse Waveform [Seite 235]
19.5 - 11.5 Equivalent Circuit [Seite 235]
19.6 - 11.6 Test Equipment [Seite 235]
19.7 - 11.7 Test Sequence and Procedure [Seite 237]
19.8 - 11.8 Failure Mechanisms [Seite 241]
19.9 - 11.9 Latchup Current Paths [Seite 242]
19.10 - 11.10 Latchup Protection Solutions [Seite 242]
19.10.1 - 11.10.1 Latchup Protection Solutions-Semiconductor Process [Seite 245]
19.10.2 - 11.10.2 Latchup Protection Solutions-Design Layout [Seite 245]
19.10.3 - 11.10.3 Latchup Protection Solutions-Circuit Design [Seite 246]
19.10.4 - 11.10.4 Latchup Protection Solutions-System Level Design [Seite 247]
19.11 - 11.11 Alternate Test Methods [Seite 248]
19.11.1 - 11.11.1 Photoemission Techniques-PICA-TLP [Seite 248]
19.11.2 - 11.11.2 Photoemission Techniques-CCD Method [Seite 250]
19.12 - 11.12 Single Event Latchup (SEL) Test Methods [Seite 250]
19.13 - 11.13 Summary and Closing Comments [Seite 250]
19.14 - Problems [Seite 253]
19.15 - References [Seite 253]
20 - Chapter 12 Electrical Overstress (EOS) [Seite 256]
20.1 - 12.1 History [Seite 256]
20.2 - 12.2 Scope [Seite 258]
20.3 - 12.3 Purpose [Seite 259]
20.4 - 12.4 Pulse Waveform [Seite 259]
20.5 - 12.5 Equivalent Circuit [Seite 259]
20.6 - 12.6 Test Equipment [Seite 260]
20.7 - 12.7 Test Procedure and Sequence [Seite 260]
20.8 - 12.8 Failure Mechanisms [Seite 262]
20.8.1 - 12.8.1 Information Gathering [Seite 262]
20.8.2 - 12.8.2 Failure Verification [Seite 263]
20.8.3 - 12.8.3 Failure Site Identification and Localization [Seite 263]
20.8.4 - 12.8.4 Root Cause Determination [Seite 264]
20.8.5 - 12.8.5 Feedback of Root Cause [Seite 264]
20.8.6 - 12.8.6 Corrective Actions [Seite 264]
20.8.7 - 12.8.7 Documentation Reports [Seite 264]
20.8.8 - 12.8.8 Statistical Analysis, Record Retention, and Control [Seite 264]
20.9 - 12.9 Electrical Overstress (EOS) Protection Circuit Solutions [Seite 266]
20.10 - 12.10 Electrical Overstress (EOS) Testing-TLP Method and EOS [Seite 275]
20.10.1 - 12.10.1 Electrical Overstress (EOS) Testing-Long Duration Transmission Line Pulse (LD-TLP) Method [Seite 276]
20.10.2 - 12.10.2 Electrical Overstress (EOS) Testing-Transmission Line Pulse (TLP) Method, EOS, and the Wunsch-Bell Model [Seite 276]
20.10.3 - 12.10.3 Electrical Overstress (EOS) Testing-Limitations of the Transmission Line Pulse (TLP) Method for the Evaluation of EOS for Systems [Seite 276]
20.10.4 - 12.10.4 Electrical Overstress (EOS) Testing-Electromagnetic Pulse (EMP) [Seite 277]
20.11 - 12.11 Electrical Overstress (EOS) Testing-DC and Transient Latchup Testing [Seite 278]
20.12 - 12.12 Summary and Closing Comments [Seite 278]
20.13 - Problems [Seite 278]
20.14 - References [Seite 279]
21 - Chapter 13 Electromagnetic Compatibility (EMC) [Seite 283]
21.1 - 13.1 History [Seite 283]
21.2 - 13.2 Purpose [Seite 284]
21.3 - 13.3 Scope [Seite 284]
21.4 - 13.4 Pulse Waveform [Seite 284]
21.5 - 13.5 Equivalent Circuit [Seite 285]
21.6 - 13.6 Test Equipment [Seite 285]
21.6.1 - 13.6.1 Commercial Test System [Seite 285]
21.6.2 - 13.6.2 Scanning Systems [Seite 286]
21.7 - 13.7 Test Procedures [Seite 287]
21.7.1 - 13.7.1 ESD/EMC Scanning Test Procedure and Method [Seite 287]
21.8 - 13.8 Failure Mechanisms [Seite 287]
21.9 - 13.9 ESD/EMC Current Paths [Seite 289]
21.10 - 13.10 EMC Solutions [Seite 290]
21.11 - 13.11 Alternative Test Methods [Seite 292]
21.11.1 - 13.11.1 Scanning Methodologies [Seite 292]
21.11.2 - 13.11.2 Testing-Susceptibility and Vulnerability [Seite 292]
21.11.3 - 13.11.3 EMC/ESD Scanning-Semiconductor Component and Populated Printed Circuit Board [Seite 293]
21.12 - 13.12 EMC/ESD Product Evaluation-IC Prequalification [Seite 293]
21.13 - 13.13 EMC/ESD Scanning Detection-Upset Evaluation [Seite 293]
21.13.1 - 13.13.1 ESD/EMC Scanning Stimulus [Seite 293]
21.14 - 13.14 EMC/ESD Product Qualification Process [Seite 294]
21.14.1 - 13.14.1 EMC/ESD Reproducibility [Seite 294]
21.14.2 - 13.14.2 EMC/ESD Failure Threshold Mapping and Histogram [Seite 294]
21.14.3 - 13.14.3 ESD Immunity Test-IC Level [Seite 294]
21.14.4 - 13.14.4 ESD Immunity Test-ATE Stage [Seite 297]
21.15 - 13.15 Alternative ESD/EMC Scanning Methods [Seite 297]
21.15.1 - 13.15.1 Alternative ESD/EMC Scanning Methods-Printed Circuit Board [Seite 297]
21.15.2 - 13.15.2 Electromagnetic Interference (EMI) Emission Scanning Methodology [Seite 300]
21.15.3 - 13.15.3 Radio Frequency (RF) Immunity Scanning Methodology [Seite 300]
21.15.4 - 13.15.4 Resonance Scanning Methodology [Seite 301]
21.15.5 - 13.15.5 Current Spreading Scanning Methodology [Seite 301]
21.16 - 13.16 Current Reconstruction Methodology [Seite 302]
21.16.1 - 13.16.1 EOS and Residual Current [Seite 302]
21.16.2 - 13.16.2 Printed Circuit Board (PCB) Trace Electromagnetic Emissions [Seite 302]
21.16.3 - 13.16.3 Test Procedure and Sequence [Seite 303]
21.17 - 13.17 Printed Circuit Board (PCB) Design EMC Solutions [Seite 303]
21.18 - 13.18 Summary and Closing Comments [Seite 306]
21.19 - Problems [Seite 307]
21.20 - References [Seite 308]
22 - Appendix A Glossary of Terms [Seite 310]
23 - Appendix B Standards [Seite 314]
23.1 - B.1 ESD Association [Seite 314]
23.2 - B.2 International Organization of Standards [Seite 315]
23.3 - B.3 IEC [Seite 315]
23.4 - B.4 RTCA [Seite 315]
23.5 - B.5 Department of Defense [Seite 315]
23.6 - B.6 Military Standards [Seite 315]
23.7 - B.7 Airborne Standards and Lightning [Seite 316]
24 - Index [Seite 317]
25 - EULA [Seite 324]

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