The Floating Point Multiplier is a wide variety for increasing accuracy, high speed and high performance in reducing delay, area and power consumption. The floating point is used for algorithms of Digital Signal Processing and Graphics. Many floating point multipliers are used to reduce the area that perform in both the single precision and the double precision in multiplication, addition and subtraction.
Here, the scientific notations sign bit, mantissa and exponent are used. The real numbers are divided into two components: fixed component of significant range (lack of dynamic range) and exponential component in floating point (largest dynamic range). The authors convert decimal to floating point and normalize the exponent part and rounding operation to reduce latency. The mantissa of two values are multiplied and the exponent part is added. The sign results with exclusive-or are obtained. Then, the final result of shift and add floating point multiplier is compared with booth multiplication.
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- Single Precision Floating PointMultiplier
- TABLE OF CONTENTS
- LIST OF TABLES
- LIST OF FIGURES
- LIST OF ABBREVIATIONS
- CHAPTER 1 INTRODUCTION
- 1.1 Format Parameters
- 1.2 Data formats for single and double precision
- 1.3 Representation of the floating point
- CHAPTER 2 LITERATURE SURVEY
- 2.1 FLOATING POINT MULTIPLIER USING VEDIC MATHEMATICS
- 2.2 FLOATING POINT OPERATION IN FAST FOURIER TRANSFORM
- 2.3 MULTIPLICATION USING CARRY SAVE MULTIPLIER
- 2.4 PARALLEL IMPLEMENTATION OF FLOATING POINT
- 2.5 NORMALIZATION OF FLOATING POINT
- 2.6 CONFIGURABLE BOOTH MULTIPLIER
- 2.7 IMPLEMENTATION ON FPGA
- 2.8 DIFFERENT MULTIPLIERS
- 2.9 DOUBLE PRECISION FLOATIG POINT
- CHAPTER 3 FLOATING POINT MULTIPLICATION OPERATION
- 3.1 FRACTION
- 3.2 REPRESENTATION OF FLOATING POINT MULTIPLICATION
- 3.3 FLOATING POINT ALGORITHM
- 3.4 MULTIPLICATION OPERATION
- 3.5 MULTIPLICATION OF MANTISSA
- 3.6 ADDING THE EXPONENTS
- 3.7 CALCULATION
- CHAPTER 4 SIMULATION IN ISE
- 4.1 VHDL SIMULATIONS FOR ADDING THE EXPONENTS
- 4.2 MULTIPLICATION
- 4.3 MULTIPLICATION OF MANTISSA
- CHAPTER 5 SCHEMATIC GENERATED IN ISE
- 5.1 Actual Schematic
- 5.2 Schematic for Mantissa
- 5.3 Magnified image of Mantissa
- 5.4 Schematic for Exponent
- 5.5 Schematic for Sign
- CHAPTER 6 SIMULATION AND CALCULATION OF POWER IN ISE DESIGN
- 6.1 SYNTHESIS POWER
- 6.2 SIMULATION FOR TOP MODULE
- CHAPTER 7 BOOTH MULTIPLICATION OPERATION
- 7.1 ALGORITHM FOR BOOTH MULTIPLICATION
- 7.2 MULTIPLICATION OPERATION
- CHAPTER 8 SIMULATION
- CHAPTER 9 SCHEMATIC GENERATED
- 9.1 Actual Schematic
- 9.2 Schematic for booth multiplier
- 9.3 Schematic for Exponent
- 9.4 Schematic for Sign
- CHAPTER 10 SIMULATION AND POWER
- 10.1 COMPARISON OF FLOATING POINT ARRAY MULTIPLIER AND BOOTH MULTIPLIER
- CHAPTER 11 IMPLEMENTATION IN FPGA KIT
- 11.1 RTL SCHEMATIC
- 11.2 PROCESS
- 11.3 THE INPUT TO CONTROL FPGA KIT
- CHAPTER 12 CONCLUSION
CHAPTER 3 FLOATING POINT MULTIPLICATION OPERATION:
The real numbers are divided into two parts. They are integer and fractional part. An integer part on the left to the radix point with using positive powers and a fraction part on the right to radix point with using negative powers. The fraction part does not give exact representation, so it divides as fixed and floating point numbers. The fixed component of significant range (lack of dynamic range) and exponential component in floating point (largest dynamic range). According to IEEE 754 2008 supports the floating point multiplier which has efficient carry saver. For the high performance of multiplier, pipe lining stages are used to increase operating frequency multiplier . [.].
Here two approaches are seen for dot product unit, floating point adder and multiplier. In general, a floating-point number consists of three main parts: sign (S), mantissa (M) and exponent ?. The precision is the important in floating point numbers. They are single precision and double precision. The double precision has the output data twice the input data when compare to the single precision.
3.2 REPRESENTATION OF FLOATING POINT MULTIPLICATION:
The IEEE standard specifies basic and extended floating-point number formats, arithmetic operations, conversions between various number formats, rounding algorithms, and floating-point exceptions. All the basic formats may be available in both hardware and software implementations. The fused dot product unit derived from floating point add sub unit. The floating point multiplier block diagram is shown. The two exponents are biased and at same time mantissa or significand combined to get parallel precision. The combined results are normalized. They done separately and multiplexers choose add and sub with XOR process. [.].
Converting decimal number to the floating point number, block diagram for floating point multiplier is shown. The two input values of exponents are added and biased. The two input mantissa values are multiplied. The two sign bits are process the XOR. Then the results of mantissa, biasing and XOR are results the floating point multiplication.
3.3 FLOATING POINT ALGORITHM:
Convert the value to binary, take fraction for separating the integral value and fractional value. This fractional part is converting by multiplication . Multiply by 2 repeatedly and harvest each one bit. It shows the decimal value to floating point. [.].
3.3.2 Adding an exponent part to binary number:
One possibility for handling numbers with fractional parts is to add bits after the decimal point: The first bit after the decimal point is the halves place, the next bit the quarters place, the next bit the eighths place and to split the bits of the representation between the places to the left of the decimal point and places to the right of the decimal point. For example, a 32-bit fixed-point representation might allocate 24 bits for the integer part and 8 bits for the fractional part. The Product of append and 2 power exponent in the end of binary numbers. [.].
The mantissa of a floating point number represents an implicit fraction whose denominator is the base raised to the power of the precision. Since the largest represent mantissa is one less than this denominator (base raise to the power of the precision), the value of the fraction is always strictly less than 1. The mathematical value of a floating point number is then the product of this fraction, the sign, and the base raised to the exponent. If the number is not normalized, then you can subtract 1 from the exponent while multiplying the mantissa by the base, and get another floating point number with the same value. Normalization consists of doing this repeatedly until the number is normalized. Two distinct normalized floating point numbers cannot be equal in value. [.].
Mantissa or significand is next to leading number which filled with zeroes on the right . When working in binary, the significand is characterized by ist width in bits. Because the most significant bit is always 1 for a normalized number, this bit is not typically stored and is called the hidden bit. Depending on the context, the hidden bit may or may not be counted towards the width of the significand. For example, the same double precision format is commonly described as having either a 53-bit significand, including the hidden bit, or a 52-bit significand, not including the hidden bit. The notion of a hidden bit only applies to binary representations. [.].
3.4 MULTIPLICATION OPERATION:
Multiplying the two input values after the normalization. The sign, exponent and mantissa are taken separately. The multiplication must take account of the integer part, implicit in normalization. The number of bits of the result is twice the size of the operands (48 bits).
Biasing is done because of exponent have to be signed values in order to represent both tiny and huge values. The exponent is biased before stored, by adjusting ist value to put it with in an unsigned range suitable range for comparison.
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