Strain Engineering in Modern Field Effect Transistors
Dept. of Electronics, Asutosh College, Kolkata, India
Generation of thermal strain while fabricating modern nano-scale Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) devices is inevitable since the standard CMOS fabrication process includes various high and low thermal stages. Different regions and materials of a MOSFET behave differently due to their difference in thermal expansion co-efficient and it leads to the generation of thermal stress within the device. Various researchers have studied the impact of strain on material and device characteristics in the last few decades through theoretical calculations, software simulations and various experiments and found that introduction of controlled strain within the transistor active region can be used to improve device performance. In this chapter, various theoretical, simulation and experimental research works on strain engineering are discussed in brief. Gradual development of this performance-enhancing technique is also included along with some of the latest reports in this field of research in modern devices.
Keywords: Strain, stress, MOSFET, FinFET, silicon-germanium (SiGe)
The last century has witnessed the growth of physics and technology to a new height. In 1930, J. E. Lilienfield invented and filed a patent  for a new device structure called MOSFET that later became an integral part of modern technology. In addition, in the field of material science, the innovation of silicon (Si) as semiconductor material opened a new field of research where the conductivity of a material can be varied according to the requirement. Particularly from the late 1940s, several researchers started publishing various theoretical research findings in this new domain of physics. From the early 1960s, the fabrication of MOSFET started, and technological development has grown very rapidly since then.
In 1965, Gordon Moore proposed his famous prediction on future technological progress that the number of transistors in an Integrated Circuit (IC) will double in every 18 months  and this law was followed by the industry for a long time by gradually reducing the dimensions of the transistor. However, as the physics of planner Si MOSFET operation started approaching its fundamental limit in reduced dimensions, scientists started looking for alternatives to dimensional reductions to sustain the technological growth. In this regard, several new semiconductor materials (e.g., GaAs, InGaAs, Graphene, MoS2 etc.) are studied in place of Si to identify the possible alternative to it. In addition, various new device structures of transistor are also explored to overcome the challenges of MOSFET in such small-scaled dimensions. Among the new transistor structures, the FinFET device has been accepted by both academia and industry due to its several advantages over the other devices. Currently the latest processors are designed by leading companies by using FinFET devices to perform the high-speed operations with improved performance.
On the other hand, there are many scientists working on the performance improvement techniques such that the improved performance of lower dimensional structures can be achieved at higher dimensional devices and the challenges of lower dimensions can be avoided. Among these performance enhancement techniques, strain engineering has been emerging as the most feasible approach, and leading companies are using this technique currently to improve the performance of their transistors. However, there are many unknown areas in strain technology, and it needs to be explored further so that it can be used in new devices also.
In this chapter, gradual discoveries of strain engineering are discussed in brief for better understanding of how this performance enhancement technique has developed. In Section 1.2, theoretical analysis of strain engineering by various researchers is discussed. Strain affects various properties of material, like the band structure, conductivity, carrier mobility, etc., and how strain-induced changes modify the device parameters are calculated by several researchers and published in reputed journals and conferences. Some of these results are discussed in brief. In Section 1.3, different simulation studies on strain engineering are included. Various simulation data are compared with theoretical and experimental data to validate the simulation results, and future technological data are predicted by using the calibrated simulators. These simulations help to forecast the output of any new device or technique which is yet to be fabricated or implemented, and in this way the simulation process helps to continue future research without worrying about the fabrication cost and time. Due to these reasons, both scientists and fabrication companies are now depending upon the data shown by properly calibrated simulation software. In Section 1.4, various experimental results on strain engineering are shown and compared with theoretical and simulated data. In the last few decades, various scientists have explored strain engineered FET devices through several experiments and these results indicate that by using this performance enhancement technique, several challenges of unstrained nano-scale transistors can be overcome. Although there are not many laboratories to fabricate these modern FETs, many published reports are available to validate the theoretically and simulated predictions in this field of strain engineering. Some of these experimental data are discussed in brief to get some idea on real-time fabrication output. Finally, in Section 1.5, a summary of this chapter is discussed in brief and some possible future research problems in this area are included.
1.2 Theory of Strain Technology
1.2.1 Stress and Strain
Strain: The result of applying force which slightly deform/misalign the atomic structure of a material.
Stress: It is the result of strain in any material.
Therefore, it can be said that by applying some external force, if the atomic arrangements of a material can be altered slightly, then interatomic force will change, and as a result, the material will be called stressed/strained material.
Now, let us consider a point P having radius vector r and position vector (x, y, z) under stable condition. When an external force is applied, the point P shifted slightly at P' and the new radius vector becomes r' and new position vector becomes (x', y', z'). The displacement is given by ; (1.1)
and this displacement gives the measure of deformation of the material under strain quantitatively. The distance between the two points can be found by using the following relation: (1.2)
is the distance in the relaxed solid.
Using the strain tensor matrix, equation (1.2) can be further written as, (1.3) (1.4)
Since the strain tensor is symmetrical in nature, the strain tensor can be diagonalized by appropriate coordinate transformation. After diagonalizing the strain tensor in a system, the modified distance ?L´ can be expressed as, (1.5)
So, for a small displacement along an axis a = ?, ?, ?, the change in length (La) becomes, (1.6)
The strain tensor in this case simplified to, (1.7)
The strain tensor, in general, can be written in terms of individual strain co-efficient (eaß), and is given by , (1.8)
The stress components for any lattice surface can be obtained from equation (1.8).
1.2.2 Stress Matrix for Biaxial and Uniaxial Stress
Now the uniaxial stress is defined as induced stress directed predominantly along any one axis. On the other hand, for biaxial stress, the induced stress is directed along two perpendicular axis direction. For  and  surface, the uniaxial stress after simplification of (1.8) becomes , (1.9) (1.10)
Since from Hooke's law it can be written that stress is proportional to strain, therefore, (1.11)
Where Cijaß are called elastic stiffness constant. As stress and strain tensors are both symmetrical in nature, so these can be written in terms of a six component array and the elastic stiffness tensor reduces to a 6×6 matrix (1.12)
In case of cubic crystal structure, the stiffness constant matrix in equation (1.12) becomes a simple form as , (1.13)
Introduction of strain technology to improve material parameters was theoretically published by several researchers in the 1950s [5-7]; however, this technology was implemented in transistor fabrication started only in the 1980s [8, 9]. The initial works of stress incorporation in the channel of a MOSFET structure was performed by using a SiGe virtual substrate and on top of that a thin Si layer was deposited as channel region . The lattice mismatch at the interface of virtual substrate and thin channel layer creates a biaxial stress in the Si channel which reduces both the inter-valley...