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The primary goal of this book is to present the design, implementation, and performance issues of AI applications and the suitability of the FPGA platform.
This book covers the features of modern Field Programmable Gate Arrays (FPGA) devices, design techniques, and successful implementations pertaining to AI applications. It describes various hardware options available for AI applications, key advantages of FPGAs, and contemporary FPGA ICs with software support. The focus is on exploiting parallelism offered by FPGA to meet heavy computation requirements of AI as complete hardware implementation or customized hardware accelerators. This is a comprehensive textbook on the subject covering a broad array of topics like technological platforms for the implementation of AI, capabilities of FPGA, suppliers' software tools and hardware boards, and discussion of implementations done by researchers to encourage the AI community to use and experiment with FPGA.
Readers will benefit from reading this book because
Audience
Researchers, industrial experts, scientists, and postgraduate students who are working in the fields of computer engineering, electronics, and electrical engineering, especially those specializing in VLSI and embedded systems, FPGA, artificial intelligence, Internet of Things, and related multidisciplinary projects.
Anuradha Thakare, PhD, is a Dean of International Relations and Professor in the Department of Computer Engineering at Pimpri Chinchwad College of Engineering, Pune, India. She has more than 22 years of experience in academics and research and has published more than 80 research articles in SCI journals as well several books.
Sheetal Bhandari, PhD, received her degree in the area of reconfigurable computing. She is a postgraduate in electronics engineering from the University of Pune with a specialization in digital systems. She is working as a professor in the Department of Electronics and Telecommunication Engineering and Dean of Academics at Pimpri Chinchwad College of Engineering. Her research area concerns reconfigurable computing and embedded system design around FPGA HW-SW Co-Design.
Preface xiii
1 Strategic Infrastructural Developments to Reinforce Reconfigurable Computing for Indigenous AI Applications 1Deepti Khurge
1.1 Introduction 2
1.2 Infrastructural Requirements for AI 2
1.3 Categories in AI Hardware 4
1.3.1 Comparing Hardware for Artificial Intelligence 8
1.4 Hardware AI Accelerators to Support RC 9
1.4.1 Computing Support for AI Application: Reconfigurable Computing to Foster the Adaptation 9
1.4.2 Reconfiguration Computing Model 10
1.4.3 Reconfigurable Computing Model as an Accelerator 11
1.5 Architecture and Accelerator for AI-Based Applications 15
1.5.1 Advantages of Reconfigurable Computing Accelerators 20
1.5.2 Disadvantages of Reconfigurable Computing Accelerators 21
1.6 Conclusion 22
References 22
2 Review of Artificial Intelligence Applications and Architectures 25Rashmi Mahajan, Dipti Sakhare and Rohini Gadgil
2.1 Introduction 25
2.2 Technological Platforms for AI Implementation-Graphics Processing Unit 27
2.3 Technological Platforms for AI Implementation-Field Programmable Gate Array (FPGA) 28
2.3.1 Xilinx Zynq 28
2.3.2 Stratix 10 NX Architecture 29
2.4 Design Implementation Aspects 30
2.5 Conclusion 32
References 32
3 An Organized Literature Review on Various Cubic Root Algorithmic Practices for Developing Efficient VLSI Computing System-Understanding Complexity 35Siba Kumar Panda, Konasagar Achyut, Swati K. Kulkarni, Akshata A. Raut and Aayush Nayak
3.1 Introduction 36
3.2 Motivation 37
3.3 Numerous Cubic Root Methods for Emergent VLSI Computing System-Extraction 45
3.4 Performance Study and Discussion 50
3.5 Further Research 50
3.6 Conclusion 59
References 59
4 An Overview of the Hierarchical Temporal Memory Accelerators 63Abdullah M. Zyarah and Dhireesha Kudithipudi
4.1 Introduction 63
4.2 An Overview of Hierarchical Temporal Memory 65
4.3 HTM on Edge 67
4.4 Digital Accelerators 68
4.4.1 Pim Htm 68
4.4.2 Pen Htm 69
4.4.3 Classic 70
4.5 Analog and Mixed-Signal Accelerators 72
4.5.1 Rcn Htm 72
4.5.2 Rbm Htm 73
4.5.3 Pyragrid 74
4.6 Discussion 76
4.6.1 On-Chip Learning 76
4.6.2 Data Movement 77
4.6.3 Memory Requirements 79
4.6.4 Scalability 80
4.6.5 Network Lifespan 82
4.6.6 Network Latency 83
4.6.6.1 Parallelism 84
4.6.6.2 Pipelining 85
4.6.7 Power Consumption 86
4.7 Open Problems 88
4.8 Conclusion 89
References 90
5 NLP-Based AI-Powered Sanskrit Voice Bot 95Vedika Srivastava, Arti Khaparde, Akshit Kothari and Vaidehi Deshmukh
5.1 Introduction 96
5.2 Literature Survey 96
5.3 Pipeline 98
5.3.1 Collect Data 98
5.3.2 Clean Data 98
5.3.3 Build Database 98
5.3.4 Install Required Libraries 98
5.3.5 Train and Validate 98
5.3.6 Test and Update 98
5.3.7 Combine All Models 100
5.3.8 Deploy the Bot 100
5.4 Methodology 100
5.4.1 Data Collection and Storage 100
5.4.1.1 Web Scrapping 100
5.4.1.2 Read Text from Image 101
5.4.1.3 MySQL Connectivity 101
5.4.1.4 Cleaning the Data 101
5.4.2 Various ML Models 102
5.4.2.1 Linear Regression and Logistic Regression 102
5.4.2.2 SVM - Support Vector Machine 103
5.4.2.3 PCA - Principal Component Analysis 104
5.4.3 Data Pre-Processing and NLP Pipeline 105
5.5 Results 106
5.5.1 Web Scrapping and MySQL Connectivity 106
5.5.2 Read Text from Image 107
5.5.3 Data Pre-Processing 108
5.5.4 Linear Regression 109
5.5.5 Linear Regression Using TensorFlow 109
5.5.6 Bias and Variance for Linear Regression 112
5.5.7 Logistic Regression 113
5.5.8 Classification Using TensorFlow 114
5.5.9 Support Vector Machines (SVM) 115
5.5.10 Principal Component Analysis (PCA) 116
5.5.11 Anomaly Detection and Speech Recognition 117
5.5.12 Text Recognition 119
5.6 Further Discussion on Classification Algorithms 119
5.6.1 Using Maximum Likelihood Estimator 119
5.6.2 Using Gradient Descent 122
5.6.3 Using Naive Bayes' Decision Theory 123
5.7 Conclusion 123
Acknowledgment 123
References 123
6 Automated Attendance Using Face Recognition 125Kapil Tajane, Vinit Hande, Rohan Nagapure, Rohan Patil and Rushabh Porwal
6.1 Introduction 126
6.2 All Modules Details 127
6.2.1 Face Detection Model 127
6.2.2 Image Preprocessing 128
6.2.3 Trainer Model 130
6.2.4 Recognizer 130
6.3 Algorithm 131
6.4 Proposed Architecture of System 131
6.4.1 Face Detection Model 132
6.4.2 Image Enhancement 132
6.4.3 Trainer Model 132
6.4.4 Face Recognition Model 133
6.5 Conclusion 134
References 134
7 A Smart System for Obstacle Detection to Assist Visually Impaired in Navigating Autonomously Using Machine Learning Approach 137Vijay Dabhade, Dnyaneshwar Dhawalshankh, Anuradha Thakare, Maithili Kulkarni and Priyanka Ambekar
7.1 Introduction 138
7.2 Related Research 138
7.3 Evaluation of Related Research 141
7.4 Proposed Smart System for Obstacle Detection to Assist Visually Impaired in Navigating Autonomously Using Machine Learning Approach 141
7.4.1 System Description 141
7.4.2 Algorithms for Proposed Work 142
7.4.3 Devices Required for the Proposed System 146
7.5 Conclusion and Future Scope 148
References 148
8 Crop Disease Detection Accelerated by GPU 151Abhishek Chavan, Anuradha Thakare, Tulsi Chopade, Jessica Fernandes and Omkar Gawari
8.1 Introduction 152
8.2 Literature Review 155
8.3 Algorithmic Study 161
8.4 Proposed System 162
8.5 Dataset 163
8.6 Existing Techniques 163
8.7 Conclusion 164
References 164
9 A Relative Study on Object and Lane Detection 167Rakshit Jha, Shruti Sonune, Mohammad Taha Shahid and Santwana Gudadhe
9.1 Introduction 168
9.2 Algorithmic Survey 168
9.2.1 Object Detection Using Color Masking 169
9.2.1.1 Color Masking 169
9.2.1.2 Modules/Libraries Used 169
9.2.1.3 Algorithm for Color Masking 169
9.2.1.4 Advantages and Disadvantages 170
9.2.1.5 Verdict 170
9.2.2 Yolo v3 Object Detection 171
9.2.2.1 Yolo V 3 171
9.2.2.2 Algorithm Architecture 171
9.2.2.3 Advantages and Disadvantages 172
9.2.2.4 Verdict 172
9.3 Yolo v/s Other Algorithms 173
9.3.1 OverFeat 173
9.3.2 Region Convolutional Neural Networks 173
9.3.3 Very Deep Convolutional Networks for Large-Scale Image Recognition 173
9.3.4 Deep Residual Learning for Image Recognition 174
9.3.5 Deep Neural Networks for Object Detection 174
9.4 Yolo and Its Version History 174
9.4.1 Yolo V 1 174
9.4.2 Fast YOLO 175
9.4.3 Yolo V 2 176
9.4.4 Yolo 9000 176
9.4.5 Yolo V 3 176
9.4.6 Yolo V 4 177
9.4.7 Yolo V 5 178
9.4.8 Pp-yolo 178
9.5 A Survey in Lane Detection Approaches 179
9.5.1 Lidar vs. Other Sensors 182
9.6 Conclusion 182
References 183
10 FPGA-Based Automatic Speech Emotion Recognition Using Deep Learning Algorithm 187Rupali Kawade, Triveni Dhamale and Dipali Dhake
10.1 Introduction 188
10.2 Related Work 189
10.2.1 Machine Learning-Based SER 189
10.2.2 Deep Learning-Based SER 193
10.3 FPGA Implementation of Proposed SER 195
10.4 Implementation and Results 199
10.5 Conclusion and Future Scope 201
References 202
11 Hardware Implementation of RNN Using FPGA 205Nikhil Bhosale, Sayali Battuwar, Gunjan Agrawal and S.D. Nagarale
11.1 Introduction 206
11.1.1 Motivation 206
11.1.2 Background 207
11.1.3 Literature Survey 207
11.1.4 Project Specification 209
11.2 Proposed Design 210
11.3 Methodology 210
11.3.1 Block Diagram Explanation 213
11.3.2 Block Diagram for Recurrent Neural Network 215
11.3.3 Textual Input Data (One Hot Encoding) 215
11.4 PYNQ Architecture and Functions 216
11.4.1 Hardware Specifications 216
11.5 Result and Discussion 216
11.6 Conclusion 217
References 217
Index 219
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