SiP System-in-Package Design and Simulation

Mentor EE Flow Advanced Design Guide
 
 
Standards Information Network (Verlag)
  • 1. Auflage
  • |
  • erschienen am 12. Juli 2017
  • |
  • 496 Seiten
 
E-Book | PDF mit Adobe-DRM | Systemvoraussetzungen
978-1-119-04601-1 (ISBN)
 
An advanced reference documenting, in detail, every step of a real System-in-Package (SiP) design flow
Written by an engineer at the leading edge of SiP design and implementation, this book demonstrates how to design SiPs using Mentor EE Flow. Key topics covered include wire bonding, die stacks, cavity, flip chip and RDL (redistribution layer), Embedded Passive, RF design, concurrent design, Xtreme design, 3D real-time DRC (design rule checking), and SiP manufacture.
Extensively illustrated throughout, System in Package Design and Simulation covers an array of issues of vital concern for SiP design and fabrication electronics engineers, as well as SiP users, including:
* Cavity and sacked dies design
* FlipChip and RDL design
* Routing and coppering
* 3D Real-Time DRC check
* SiP simulation technology
* Mentor SiP Design and Simulation Platform
Designed to function equally well as a reference, tutorial, and self-study, System in Package Design and Simulation is an indispensable working resource for every SiP designer, especially those who use Mentor design tools.
  • Englisch
  • New York
  • |
  • Singapur
John Wiley & Sons Inc
  • Für Beruf und Forschung
  • 87,29 MB
978-1-119-04601-1 (9781119046011)
weitere Ausgaben werden ermittelt
Mr. Suny Li (Li Yang) is a SiP/PCB Technical Specialist in China; he now works in AcconSys Technology Co. Ltd, (a Mentor Authorized Distributor for China). Suny has guided and consulted on dozens of SiP projects in China, accumulating plentiful experience in SiP design and simulation. Suny has 10 years' experience in and knowledge of Application Engineer for Mentor, especially in SiP/PCB design and simulation. Before this, Suny worked in the Chinese Academy of Science and SIEMENS for several years. He has more than seven years' experience in hardware design (HW system design, PCB layout, high-speed signal integrity, power integrity, EMI, etc.). In the course of his work, Suny has published papers and acquired four patents, and he continues with this work. Suny is a senior member of the Chinese Institute of Electronics (CIE) and a member of the IEEE. Suny graduated from Beijing University of Aeronautics & Astronautics (BUAA) in 2000, receiving Master's and Bachelor's degrees in Science and Technology of Aeronautics & Astronautics.
  • Cover
  • Title Page
  • Copyright
  • Contents
  • About the Author
  • Preface
  • Chapter 1 SiP Design and Simulation Platform
  • 1.1 From package to SiP
  • 1.2 The development of mentor SiP design technology
  • 1.3 The mentor SiP design and simulation platform
  • 1.3.1 SiP platform introduction
  • 1.3.2 Schematic input
  • 1.3.3 Concurrent system design
  • 1.3.4 SiP board design
  • 1.3.5 Signal integrity and power integrity simulation
  • 1.3.6 Thermal analysis
  • 1.3.7 The advantages of the mentor SiP design and simulation platform
  • 1.3.7.1 Characteristics of mentor SiP design and simulation platform
  • 1.3.7.2 Design areas of mentor SiP design and simulation platform
  • 1.4 The introduction of the finished project
  • Chapter 2 Introduction to Package
  • 2.1 Definition and function of package
  • 2.2 Development of packaging technology
  • 2.3 SiP and Related Technologies
  • 2.3.1 The appearance of SiP technology
  • 2.3.2 SoC and SiP
  • 2.3.3 SiP-related technologies
  • 2.4 The development of the package market
  • 2.5 Package manufacturers
  • 2.5.1 Traditional package manufacturers
  • 2.5.2 New SiP manufacturers in different areas
  • 2.6 Bare chip suppliers
  • Chapter 3 The SiP Production Process
  • 3.1 BGA: The mainstream SiP package form
  • 3.2 The SiP package production process
  • 3.3 Three key elements of SiP
  • Chapter 4 New Package Technologies
  • 4.1 TSV (Through Silicon Via) technology
  • 4.1.1 TSV introduction
  • 4.1.2 TSV technical characteristics
  • 4.1.3 TSV application and prospects
  • 4.2 Integrated passive device (IPD) technology
  • 4.2.1 IPD introduction
  • 4.2.2 The advantages of IPD
  • 4.3 Package on package (PoP) technology
  • 4.3.1 The limitations of 3D SiP
  • 4.3.2 The application of PoP
  • 4.3.3 The emphasis in PoP design
  • 4.4 Apple A8 processor - an example of a PoP product
  • Chapter 5 SiP Design and Simulation Flow
  • 5.1 SiP design and simulation flow
  • 5.2 Design and simulation process in Mentor EE Flow
  • 5.2.1 Library creation
  • 5.2.2 Schematic design
  • 5.2.3 Layout design
  • 5.2.4 Design simulation
  • Chapter 6 Central Library
  • 6.1 The structure of the central library
  • 6.2 Introduction to the Dashboard
  • 6.3 Schematic symbol creation
  • 6.4 Bare chip cell creation
  • 6.4.1 Create bare chip padstack
  • 6.4.2 Create bare chip cell
  • 6.5 BGA cell creation
  • 6.5.1 Create BGA padstack
  • 6.5.2 Create BGA cell manually
  • 6.5.2.1 Tips for renaming the pin numbers
  • 6.5.2.2 View layers defined in padstacks
  • 6.5.3 Create BGA cell with Die Wizard
  • 6.5.4 LP Wizard professional library tool
  • 6.6 Part creation
  • 6.7 Create cell via part
  • Chapter 7 Schematic Input
  • 7.1 Netlist input
  • 7.2 Basic schematic input
  • 7.2.1 Start DxDesigner
  • 7.2.1.1 General toolbar
  • 7.2.1.2 Digital/analog simulation toolbar
  • 7.2.1.3 RF circuit design toolbar
  • 7.2.2 Create new project
  • 7.2.2.1 How to create a new project
  • 7.2.2.2 Net connection and draw toolbar
  • 7.2.3 Schematic design check
  • 7.2.4 Design rules setup
  • 7.2.5 Package design
  • 7.2.5.1 Packaging options
  • 7.2.5.2 PDB Extraction Options
  • 7.2.6 Partlist output
  • 7.2.7 Chinese input in schematic
  • 7.2.8 Enter layout environment
  • 7.3 Schematic input based on DxDataBook
  • 7.3.1 DxDataBook introduction
  • 7.3.2 DxDataBook usage
  • 7.3.3 Check and update component properties
  • Chapter 8 Multi-board Project Management and Concurrent Schematic Design
  • 8.1 Multi-board project management
  • 8.1.1 SiP and PCB collaborative design
  • 8.1.2 Multi-board project design flow
  • 8.2 Concurrent schematic design
  • 8.2.1 Concurrent design thinking
  • 8.2.2 Operating method for concurrent schematic design
  • Chapter 9 Layout Creation and Setting
  • 9.1 Create layout template
  • 9.1.1 Layout template definition
  • 9.1.2 Create SiP layout template
  • 9.2 Create layout project
  • 9.2.1 Create new SiP project
  • 9.2.2 Enter layout design environment
  • 9.3 Layout-related setup and operation
  • 9.3.1 Introduction to layout license control
  • 9.3.2 Mouse handling
  • 9.3.3 Three kinds of commonly used operating modes
  • 9.3.3.1 Select parts
  • 9.3.3.2 Select nets
  • 9.3.3.3 Select draw objects
  • 9.3.4 Display control
  • 9.3.4.1 Layer Tab, General Tab, Part Tab
  • 9.3.4.2 Net tab, Hazard tab, Groups tab
  • 9.3.5 Editor control
  • 9.3.5.1 Common settings
  • 9.3.5.2 Place tab
  • 9.3.5.3 Route tab
  • 9.3.5.4 Grids tab
  • 9.3.6 Setup parameters
  • 9.4 Substrate layout
  • 9.4.1 Component Placement
  • 9.4.2 Automatic optimization of net connections
  • 9.5 eDxD view
  • 9.6 Input Chinese characters in layout
  • 9.6.1 Manually input Chinese characters
  • 9.6.2 Import Chinese words from DXF file
  • Chapter 10 Constraint Rules Management
  • 10.1 CES - Constraint Editor System
  • 10.2 Scheme
  • 10.2.1 Create scheme
  • 10.2.2 Use scheme in layout
  • 10.3 Define layer stackup and parameters
  • 10.4 Net Class
  • 10.4.1 Create net class and assign nets to net class
  • 10.4.2 Define net class rules
  • 10.5 Clearance rules
  • 10.5.1 Clearance rule creation and setup
  • 10.5.2 General clearance rules
  • 10.5.3 Net class to net class clearance rules
  • 10.6 Constraint class
  • 10.6.1 Create constraint class and assign net to constraint class
  • 10.6.2 Constraint classes classification
  • 10.6.3 Edit constraint groups
  • 10.7 Update CES data with layout
  • Chapter 11 Wire Bond Design
  • 11.1 Wire bond overview
  • 11.2 Bond wire model
  • 11.2.1 Bond wire model creation
  • 11.2.2 Bond wire properties
  • 11.3 Wire bond toolbar
  • 11.3.1 Add bond wire manually
  • 11.3.2 Move and rotate bond pad
  • 11.3.3 Wire bond and power ring generator
  • 11.3.4 Wire bond rule setting
  • 11.3.4.1 Settings for part
  • 11.3.4.2 Settings for die pin
  • 11.3.4.3 Add multiple bond wires between die pin and bond pad
  • 11.3.4.4 Fan out to multiple bond pads from single die pin
  • 11.3.4.5 Bond multiple die pins to one bond pad
  • 11.3.4.6 Die-to-die bonding
  • 11.3.5 Wire model editor
  • Chapter 12 Cavity and Chip Stack Design
  • 12.1 Cavity
  • 12.1.1 Cavity definition
  • 12.1.2 Cavity creation
  • 12.1.3 Place component into cavity
  • 12.1.4 Bonding in cavity
  • 12.1.5 Embedded cavity design and embedding chip into substrate
  • 12.2 Chip stack
  • 12.2.1 The concept of chip stack
  • 12.2.2 Chip stack creation
  • 12.2.3 Stack chips side by side
  • 12.2.4 Adjust relative position of chips in stack
  • 12.2.5 Chip stack bonding
  • Chapter 13 Flip Chip and RDL Design
  • 13.1 The concept and characteristics of flip chip
  • 13.2 The RDL concept
  • 13.3 RDL design
  • 13.3.1 Create bare die and RDL library
  • 13.3.2 RDL schematic design
  • 13.3.3 RDL layout design
  • 13.4 Flip chip design
  • 13.4.1 Flip chip schematic design
  • 13.4.2 Flip chip layout design
  • Chapter 14 Route and Plane
  • 14.1 Routing
  • 14.1.1 Introduction to routing
  • 14.1.2 Manual route
  • 14.1.3 Plow modes
  • 14.1.4 Gloss modes
  • 14.1.5 Fix and lock
  • 14.1.6 Layer switching
  • 14.1.7 Move trace and via
  • 14.1.8 Circuit copy
  • 14.1.9 Semi-automatic route
  • 14.1.10 Auto route
  • 14.1.11 Route differential pairs
  • 14.1.12 Length control in routing
  • 14.2 Plane
  • 14.2.1 Plane definition
  • 14.2.2 Plane setting
  • 14.2.2.1 Plane classes parameters
  • 14.2.2.2 Plane assignments
  • 14.2.3 Draw plane shape
  • 14.2.4 Modify plane shape
  • 14.2.5 Generate negative plane data
  • 14.2.6 Delete plane data
  • 14.2.7 Verify plane data
  • Chapter 15 Embedded Passives Design
  • 15.1 The development of embedded technology
  • 15.1.1 Discrete embedded technology
  • 15.1.2 Planar embedded technology
  • 15.2 Process and material for embedded passives
  • 15.2.1 Embedding processes
  • 15.2.1.1 Additive resistors
  • 15.2.1.2 Subtractive resistors
  • 15.2.1.3 Capacitors
  • 15.2.2 Embedding materials
  • 15.2.2.1 Capacitor materials
  • 15.2.2.2 Conductor materials
  • 15.2.2.3 Insulator materials
  • 15.2.2.4 Resistor materials
  • 15.2.3 The nonlinear characteristics of resistance materials
  • 15.3 Resistor and capacitor automatic synthesis
  • 15.3.1 Preparation for automatic synthesis
  • 15.3.2 Resistor automatic synthesis
  • 15.3.3 Capacitor automatic synthesis
  • Chapter 16 RF Circuit Design
  • 16.1 RF SiP Technology
  • 16.2 Mentor RF design flow
  • 16.3 RF schematic design
  • 16.3.1 RF shapes library configuration
  • 16.3.2 RF schematic toolbar
  • 16.3.3 RF schematic design
  • 16.4 RF parameter transfer between schematic and layout
  • 16.5 RF layout design
  • 16.5.1 RF toolkit in layout
  • 16.5.2 Three kinds of RF unit
  • 16.5.3 Add and edit meander
  • 16.5.4 RF Control window
  • 16.5.5 Create custom RF shape
  • 16.5.6 RF via
  • 16.5.7 RF group
  • 16.5.8 Other RF edit functions
  • 16.6 Connect RF simulation tools and transfer data
  • 16.6.1 Connect RF simulation tools
  • 16.6.2 Layout RF data transmission
  • 16.6.3 Schematic RF data transmission
  • Chapter 17 Concurrent Layout Design
  • 17.1 Concurrent layout design technology - Xtreme
  • 17.2 Xtreme configuration
  • 17.3 Start Xtreme concurrent design
  • 17.4 Matters to note in Xtreme
  • Chapter 18 3D Real-time DRC
  • 18.1 Wire Model Editor 3D display and DRC
  • 18.1.1 Wire Model Editor 3D display
  • 18.1.2 Wire Model Editor 3D DRC
  • 18.2 3D Viewer display and DRC
  • 18.2.1 3D Viewer introduction
  • 18.2.2 Real-time check in 3D Viewer
  • 18.2.3 3D Simulation of SiP production processing
  • 18.2.4 Import 3D mechanical data
  • 18.2.5 Real-time DRC in 3D Viewer
  • Chapter 19 Design Review
  • 19.1 Online DRC
  • 19.2 Batch DRC
  • 19.2.1 DRC settings
  • 19.2.2 Connectivity and special rules
  • 19.2.3 Batch DRC scheme
  • 19.3 Review hazards
  • 19.4 Verify design library
  • Chapter 20 Manufacturing Data Output
  • 20.1 Drill and Gerber data output
  • 20.1.1 Drill data output
  • 20.1.2 Gerber machine format
  • 20.1.3 Gerber data output
  • 20.1.4 Import and check Gerber data
  • 20.2 Other Manufacturing Data Output
  • 20.2.1 Component and bond wire coordinate file output
  • 20.2.2 DXF file export
  • 20.2.3 Layout design status output
  • 20.2.4 BOM output
  • Chapter 21 SiP Simulation Technology
  • 21.1 SiP simulation technology overview
  • 21.2 Signal integrity simulation
  • 21.2.1 HyperLynx SI simulation tool introduction
  • 21.2.2 HyperLynx SI simulation example
  • 21.3 Power integrity simulation
  • 21.3.1 HyperLynx PI simulation tool introduction
  • 21.3.2 HyperLynx PI simulation example
  • 21.4 Thermal analysis
  • 21.4.1 HyperLynx Thermal introduction
  • 21.4.2 HyperLynx Thermal simulation example
  • 21.5 EMI/EMC Analysis
  • 21.5.1 HyperLynx DRC introduction
  • 21.5.2 HyperLynx DRC example
  • 21.6 Mixed-signal simulation introduction
  • Reference Materials
  • Postscript and Thanks
  • Index
  • Supplemental Images
  • EULA

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