Boolean Circuit Rewiring

Bridging Logical and Physical Designs
 
 
John Wiley & Sons Inc (Verlag)
  • 1. Auflage
  • |
  • erschienen am 6. Januar 2016
  • |
  • 235 Seiten
 
E-Book | PDF mit Adobe DRM | Systemvoraussetzungen
978-1-118-75013-1 (ISBN)
 

Demonstrates techniques which will allow rewiring rates of over 95%, enabling adoption of deep sub-micron chips for industrial applications

Logic synthesis is an essential part of the modern digital IC design process in semi-conductor industry. This book discusses a logic synthesis technique called 'rewiring' and its latest technical advancement in term of rewirability. Rewiring technique has surfaced in academic research since 1993 and there is currently no book available on the market which systematically and comprehensively discusses this rewiring technology. The authors cover logic transformation techniques with concentration on rewiring. For many decades, the effect of wiring on logic structures has been ignored due to an ideal view of wires and their negligible role in the circuit performance. However in today's semiconductor technology wiring is the major player in circuit performance degeneration and logic synthesis engines can be improved to deal with this through wire-based transformations. This book introduces the automatic test pattern generation (ATPG)-based rewiring techniques, which are recently active in the realm of logic synthesis/verification of VLSI/SOC designs.

  • Unique comprehensive coverage of semiconductor rewiring techniques written by leading researchers in the field
  • Provides complete coverage of rewiring from an introductory to intermediate level
  • Rewiring is explained as a flexible technique for Boolean logic synthesis, introducing the concept of Boolean circuit transformation and testing, with examples
  • Readers can directly apply the described techniques to real-world VLSI design issues
  • Focuses on the automatic test pattern generation (ATPG) based rewiring methods although some non-ATPG based rewiring methods such as graph based alternative wiring (GBAW), and 'set of pairs of functions to be distinguished' (SPFD) based rewiring are also discussed

A valuable resource for researchers and postgraduate students in VLSI and SoC design, as well as digital design engineers, EDA software developers, and design automation experts that specialize in the synthesis and optimization of logical circuits.

  • Englisch
  • Hoboken
  • |
  • Singapur
  • Für Beruf und Forschung
  • 5,19 MB
978-1-118-75013-1 (9781118750131)
1118750136 (1118750136)
weitere Ausgaben werden ermittelt
  • Cover
  • Title Page
  • Copyright
  • Contents
  • List of Figures
  • List of Tables
  • Preface
  • Introduction
  • Chapter 1 Preliminaries
  • 1.1 Boolean Circuits
  • 1.2 Redundancy and Stuck-at Faults
  • 1.3 Automatic Test Pattern Generation (ATPG)
  • 1.4 Dominators
  • 1.5 Mandatory Assignments and Recursive Learning
  • 1.6 Graph Theory and Boolean Circuits
  • References
  • Chapter 2 Concept of Logic Rewiring
  • 2.1 What is Rewiring?
  • 2.2 ATPG-based Rewiring Techniques
  • 2.2.1 Add-First
  • 2.2.2 Delete-First
  • 2.3 Non-ATPG-based Rewiring Techniques
  • 2.3.1 Graph-based Alternate Wiring (GBAW)
  • 2.3.2 SPFD
  • 2.4 Why are Rewiring Techniques Important?
  • References
  • Chapter 3 Add-First and Non-ATPG-Based Rewiring Techniques
  • 3.1 Redundancy Addition and Removal (RAR)
  • 3.1.1 RAMBO
  • 3.1.2 REWIRE
  • 3.1.3 RAMFIRE
  • 3.1.4 Comparison Between RAR-Based Rewiring Techniques
  • 3.2 Node-Based Network Addition and Removal (NAR)
  • 3.2.1 Node Merging
  • 3.2.2 Node Addition and Removal
  • 3.3 Other Rewiring Techniques
  • 3.3.1 SPFD-Based Rewiring
  • References
  • Chapter 4 Delete-First Rewiring Techniques
  • 4.1 IRRA
  • 4.1.1 Destination of Alternative Wires
  • 4.1.2 Source of Alternative Wires
  • 4.2 ECR
  • 4.2.1 Destination of Alternative Wires
  • 4.2.2 Source of Alternative Wires
  • 4.2.3 Overview of the Approach of Error-Cancellation-Based Rewiring
  • 4.2.4 Complexity Analysis of ECR
  • 4.2.5 Comparison Between ECR and Other Resynthesis Techniques
  • 4.2.6 Experimental Result
  • 4.3 FECR
  • 4.3.1 Error Flow Graph Construction
  • 4.3.2 Destination Node Identification
  • 4.3.3 Source Node Identification
  • 4.3.4 ECR is a Special Case of FECR
  • 4.3.5 Complexity Analysis of FECR
  • 4.3.6 Experimental Result
  • 4.4 Cut-Based Error Cancellation Rewiring
  • 4.4.1 Preliminaries
  • 4.4.2 Error Frontier
  • 4.4.3 Cut-Based Error Cancellation Rewiring
  • 4.4.4 Verification of Alternative Wires
  • 4.4.5 Complexity Analysis of CECR
  • 4.4.6 Relationship Between ECR, FECR, and CECR
  • 4.4.7 Extending CECR for n-to-m Rewiring
  • 4.4.8 Speedup for CECR
  • 4.4.9 Experimental Results
  • References
  • Chapter 5 Applications
  • 5.1 Area Reduction
  • 5.1.1 Preliminaries
  • 5.1.2 Our Methodology ("Long tail" vs "Bump tail" Curves)
  • 5.1.3 Details of our Approach
  • 5.1.4 Experimental Results
  • 5.2 Postplacement Optimization
  • 5.2.1 Wire-Length-Driven Rewiring-Based Postplacement Optimization
  • 5.2.2 Timing-Driven Rewiring-Based Postplacement Optimization
  • 5.3 ECO Timing Optimization
  • 5.3.1 Preliminaries
  • 5.3.2 Nego-Rout Operation
  • 5.3.3 Path-Restructuring Operation
  • 5.3.4 Experimental Results
  • 5.4 Area Reduction in FPGA Technology Mapping
  • 5.4.1 Incremental Logic Resynthesis (ILR): Depth-Oriented Mode
  • 5.4.2 Incremental Logic Resynthesis (ILR): Area-Oriented Mode
  • 5.4.3 Experimental Results
  • 5.4.4 Conclusion
  • 5.5 FPGA Postlayout Routing Optimization
  • 5.5.1 Optimization by Alternative Functions
  • 5.5.2 Optimization with Mapping-to-Routing Logic Rewirings
  • 5.5.3 Optimization by SPFD-Based Rewiring
  • 5.6 Logic Synthesis for Low Power Using Clock Gating and Rewiring
  • 5.6.1 Mechanism of Clock Gating
  • 5.6.2 Rewiring-Based Optimization
  • References
  • Chapter 6 Summary
  • Index
  • EULA

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