This book brings together a selection of the best papers from the nineteenth edition of the Forum on specification and Design Languages Conference (FDL), which took place on September 14-16, 2016, in Bremen, Germany. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems.
Franco Fummi received the Laurea degree in Electronic Engineering at Politecnico di Milano in 1990 and the Ph.D.in Electronic and Communication Engineering in 1994 at Politecnico di Milano. In 1993 he was Research Assistant at the department of Computer Science of the University of Victoria (B.C.). In 1996 he obtained the position of Assistant Professor in Computer Science at the Dipartimento di Elettronica e Informazione of Politecnico di Milano where he remained until October 1998. In July 1998 he obtained the position of Associate Professor in Computer Architecture at the Computer Science Department of Università di Verona. Since March 2001 he is Full Professor in Computer Architecture at the Computer Science Department of Università di Verona He is leading the Electronic Systems Design (ESD) group of the Università di Verona (http://esd.sci.univr.it), currently composed of more than 20 people and working on hardware description languages and electronic design automation methodologies for modeling, verification, testing and optimization of embedded systems.
From 2002 to 2006, Robert Wille studied Computer Science (Diploma) at the University of Bremen. After successfully completing his doctorate in 2009 (summa cum laude), he worked as postdoc at the University of Bremen and, since 2013, as Senior Researcher in the Cyber-Physical Systems department of the German Research Center for Artificial Intelligence (DFKI). Besides that, he served as lecturer at the University of Applied Science Bremen from 2010 to 2012 and was guest professor for Technical Computer Science at the University of Potsdam in 2012 as well as for Embedded Systems at the Technical University of Dresden in 2013/2014. In 2014, he completed his habilitation and, since October 2015, he is full professor at the Johannes Kepler University Linz and head of the Department for Integrated Circuit and System Design.
Robert Wille's expertise is in the development of design technologies for various application areas - with a particular focus on the design, verification, and test of circuits and systems. He considers thereby conventional as well as emerging computing technologies such as quantum computation, reversible circuits, or microfluidic biochips. Since 2007, Robert Wille published more than 150 journal and conference papers in this area (including top-notch venues such as DAC, DATE, ICCAD, ASP-DAC, MoDELS, or TCAD) and was repeatedly awarded (e.g. with a Best Paper Award at the International Conference on Computer-Aided Design in 2013 and the Forum on Specification and Design Languages in 2010).
Robert Wille served as Guest Editor for the ACM Journal on Emerging Technologies in Computing Systems (JETC), Springer's Lecture Notes in Computer Science (LNCS), and the Journal for Multiple-Valued Logic and Soft Computing (MVLSC). Additionally, he was PC Chair at the Forum on Description Languages, the Conference on Reversible Computation, and the International Symposium on Multiple-Valued Logic (ISMVL) as well as served as Subcommittee Chair at the Asia and South Pacific Design Automation Conference (ASP-DAC), was in program committees of numerous conferences such as ASP-DAC, DAC, ICCAD, ISMVL, etc., and organized several conferences, tutorials, Dagstuhl seminars, workshops, and special sessions.
Chapter1. Knowing Your AMS System's Limits: System Acceptance Region Exploration by Using Automated Model Refinement and Accelerated Simulation.- Chapter2. Designing Reliable Cyber-Physical Systems.- Chapter3. On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-based Error Effect Simulation - A Case Study.- Chapter4. Selective Abstraction and Stochastic Methods for Scalable Power Modelling of Heterogeneous Systems.- Chapter5. Feature based State Space Coverage of Analog Circuits.- Chapter6. Error-free Near-threshold Adiabatic CMOS Logic in Presence of Process Variation.