Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing

 
 
John Wiley & Sons Inc (Verlag)
  • erschienen am 27. Januar 2016
  • |
  • 352 Seiten
 
E-Book | PDF mit Adobe DRM | Systemvoraussetzungen
978-1-118-86925-3 (ISBN)
 
Nanomagnetic and spintronic computing devices are strong contenders for future replacements of CMOS. This is an important and rapidly evolving area with the semiconductor industry investing significantly in the study of nanomagnetic phenomena and in developing strategies to pinpoint and regulate nanomagnetic reliably with a high degree of energy efficiency. This timely book explores the recent and on-going research into nanomagnetic-based technology.
Key features:
* Detailed background material and comprehensive descriptions of the current state-of-the-art research on each topic.
* Focuses on direct applications to devices that have potential to replace CMOS devices for computing applications such as memory, logic and higher order information processing.
* Discusses spin-based devices where the spin degree of freedom of charge carriers are exploited for device operation and ultimately information processing.
* Describes magnet switching methodologies to minimize energy dissipation.
* Comprehensive bibliographies included for each chapter enabling readers to conduct further research in this field.
Written by internationally recognized experts, this book provides an overview of a rapidly burgeoning field for electronic device engineers, field-based applied physicists, material scientists and nanotechnologists. Furthermore, its clear and concise form equips readers with the basic understanding required to comprehend the present stage of development and to be able to contribute to future development. Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing is also an indispensable resource for students and researchers interested in computer hardware, device physics and circuits design.
1. Auflage
  • Englisch
  • New York
  • |
  • Großbritannien
  • Für Beruf und Forschung
  • 22,42 MB
978-1-118-86925-3 (9781118869253)
1118869257 (1118869257)
weitere Ausgaben werden ermittelt
Professor Supriyo Bandyopadhyay, Virginia Commonwealth University, Virginia, USA
Supriyo Bandyopadhyay is Commonwealth Professor of Electrical and Computer Engineering at Virginia Commonwealth University where he directs the Quantum Device Laboratory. Prof. Bandyopadhyay has authored and co-authored over 300 research publications and he is currently a member of the editorial board of seven international journals. He is the current Chair of the Institute of Electrical and Electronics Engineers (IEEE) Technical Committee on Spintronics (Nanotechnology Council), and past-chair of the Technical Committee on Compound Semiconductor Devices and Circuits (Electron Device Society). He has been an IEEE Electron Device Society Distinguished Lecturer and served as a Vice President of the IEEE Nanotechnology Council. Prof. Bandyopadhyay is a Fellow of the Institute of Electrical and Electronics Engineers, the Institute of Physics, American Physical Society, the Electrochemical Society and the American Association for the Advancement of Science.
Professor Jayasimha Atulasimha, Virginia Commonwealth University, Virginia, USA
Jayasimha Atulasimha is Qimonda Associate Professor of Mechanical and Nuclear Engineering with a courtesy appointment in Electrical and Computer Engineering at the Virginia Commonwealth University, where he directs the Magnetism, Magnetic Materials and Magnetic Devices (M³) laboratory. He has authored or coauthored over 60 scientific articles including more than 40 journal publications on magnetostrictive materials, magnetization dynamics, and nanomagnetic computing and has given several invited talks at conferences, workshops and universities in the USA and abroad on these topics. His research interests include nanomagnetism, spintronics, magnetostrictive materials and nanomagnet-based computing devices. He received the NSF CAREER Award for
2013-2018. He currently serves on the Technical Committees for Spintronics, IEEE Nanotechnology Council, ASME Adaptive Structures and Material Systems, Device Research Conference (DRC), and as a Focus Topic organizer for the APS topical group on magnetism (GMAG). He is a member of ASME, APS and an IEEE Senior Member.
  • Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing
  • Contents
  • About the Editors and Acknowledgments
  • Jayasimha Atulasimha
  • Supriyo Bandyopadhyay
  • Acknowledgments
  • List of Contributors
  • Foreword
  • Preface
  • 1 Introduction to Spintronic and Nanomagnetic Computing Devices
  • 1.1 Spintronic Devices
  • 1.2 Nanomagnetic Devices
  • 1.2.1 Use of Spin Torque to Switch Nanomagnets
  • 1.2.2 Other Methodologies for Switching Nanomagnets
  • 1.3 Thinking beyond Traditional Boolean Logic
  • References
  • 2 Potential Applications of all Electric Spin Valves Made of Asymmetrically Biased Quantum Point Contacts
  • 2.1 Introduction
  • 2.2 Quantum Point Contacts
  • 2.3 Spin Orbit Coupling
  • 2.3.1 Rashba SOC (RSOC)
  • 2.3.2 Dresselhaus SOC (DSOC)
  • 2.3.3 Lateral Spin-Orbit Coupling (LSOC)
  • 2.4 Importance of Spin Relaxation in 1D Channels
  • 2.5 Observation of a 0.5 Conductance Plateau in Asymmetrically Biased QPCs in the Presence of LSOC
  • 2.5.1 Early Experimental Results Using InAs QPCs
  • 2.5.2 NEGF Conductance Calculations
  • 2.5.3 Spin Texture Associated with Conductance Anomalies in QPCs
  • 2.5.4 Prospect for Generation of Spin Polarized Current at Higher Temperature
  • 2.5.5 Observation of Other Anomalous Conductance Plateaus in an Asymmetrically Biased InAs/In0.52 Al0.48 as QPCs
  • 2.6 Intrinsic Bistability near Conductance Anomalies
  • 2.6.1 Experimental Results
  • 2.6.2 NEGF Simulations
  • 2.7 QPC Structures with Four In-plane SGs: Toward an All Electrical Spin Valve
  • 2.7.1 Preliminary Results on Four-gate QPCs
  • 2.7.2 Experiments
  • 2.7.3 Onset of Hysteresis and Negative Resistance Region
  • 2.8 Future Work
  • 2.9 Summary
  • Acknowledgments
  • References
  • 3 Spin-Transistor Technology for Spintronics/CMOS Hybrid Logic Circuits and Systems
  • 3.1 Spin-Transistor and Pseudo-Spin-Transistor
  • 3.1.1 Spin - MOSFET
  • 3.1.2 Pseudo-Spin-MOSFET
  • 3.2 Energy-Efficient Logic Applications of Spin-Transistors
  • 3.2.1 Power Gating with Nonvolatile Retention
  • 3.2.2 Nonvolatile Bistable Circuits
  • 3.2.3 Break-even Time
  • 3.3 Nonvolatile SRAM Technology
  • 3.3.1 Static Noise Margin of Nonvolatile SRAM
  • 3.3.2 Energy Performance of NV-SRAM
  • 3.4 Application of Nonvolatile Bistable Circuits for Memory Systems
  • References
  • 4 Spin Transfer Torque: A Multiscale Picture
  • 4.1 Introduction
  • 4.1.1 Background
  • 4.1.2 STT Modeling: An Integrated Approach
  • 4.2 The Physics of Spin Transfer Torque
  • 4.2.1 Free-Electron Model for Magnetic Tunnel Junction
  • 4.3 First Principles Evaluation of TMR and STT
  • 4.3.1 The TMR Effect in the MgO Barrier
  • 4.3.2 Currents and Torques in NEGF
  • 4.3.3 First Principles Results on Spin Transfer Torque
  • 4.4 Magnetization Dynamics
  • 4.4.1 Landau-Lifshitz-Gilbert Equation
  • 4.4.2 Spin Torque Switching in Presence of Thermal Fluctuations
  • 4.4.3 Including Thermal Fluctuations: Stochastic LLG vs Fokker Planck
  • 4.5 Summary: Multiscaling from Atomic Structure to Error Rate
  • Acknowledgments
  • References
  • 5 Magnetic Tunnel Junction Based Integrated Logics and Computational Circuits
  • 5.1 Introduction
  • 5.2 GMR Based Field Programmable Devices
  • 5.3 MTJ Based Field Programmable Devices
  • 5.3.1 MTJ Structure and TMR Ratio
  • 5.3.2 MTJ Based Magneto-Logic
  • 5.3.3 Utilization of STT in MTJ Based Magneto-Logic
  • 5.4 Information Transformation between Gates
  • 5.4.1 Direct Communication Using Charge Current
  • 5.4.2 Magnetic Domain Walls for Information Transferring
  • 5.5 MTJ Based Logic-in-Memory Devices
  • 5.6 Magnetic Quantum Cellular Automata
  • 5.6.1 Introduction and Background
  • 5.6.2 Experimental Demonstrations
  • 5.7 All-Spin Based Magnetic Logic
  • 5.7.1 Nonlocal Lateral Spin Valve Background
  • 5.7.2 Critical Parameters for Operation
  • 5.7.3 Selected Review of Experimental Demonstrations
  • 5.7.4 Applications to All-Spin Logic Devices
  • 5.8 Summary
  • Acknowledgment
  • References
  • 6 Magnetization Switching and Domain Wall Motion Due to Spin Orbit Torque
  • 6.1 Introduction
  • 6.2 Theory
  • 6.2.1 Rashba Effect
  • 6.2.2 Spin Hall Effect
  • 6.3 Magnetic Switching Driven by Spin Orbit Torque
  • 6.4 Domain Wall Motion Driven by Spin Orbit Torque
  • 6.5 Applications of Spin Orbit Torque
  • 6.6 Conclusion
  • References
  • 7 Magnonic Logic Devices
  • 7.1 Introduction
  • 7.2 Magnonic Logic Devices
  • 7.3 Spin Wave-Based Logic Gates and Architectures
  • 7.4 Discussion and Summary
  • References
  • 8 Strain Mediated Magnetoelectric Memory
  • 8.1 Introduction
  • 8.2 Concept of Unequivocal Strain- or Stress-Switched Nanomagnetic Memory
  • 8.2.1 Magnetic Configuration and Equilibrium Positions
  • 8.2.2 Quasi-Static Stress-Mediated Switching
  • 8.3 LLG Simulations - Macrospin Model
  • 8.3.1 Landau-Lifshitz-Gilbert Equation and Effective Magnetic Field
  • 8.3.2 Memory Parameters
  • 8.3.3 Results of the Macrospin Model
  • 8.4 LLG Simulations - Eshelby Approach
  • 8.4.1 Geometry of the Memory Element
  • 8.4.2 Coupling with the External Magnetic Field
  • 8.4.3 Coupling with the External Electric Field and Elastic Stress
  • 8.4.4 Static Behavior of the System
  • 8.4.5 Dynamic Behavior of the System
  • 8.5 Stochastic Error Analysis
  • 8.5.1 Statistical Mechanics of Magnetization in a Single-Domain Particle
  • 8.5.2 Switching Process within the Magnetoelectric Memory
  • 8.6 Preliminary Experimental Results
  • 8.6.1 Piezoelectric Actuator with in-Plane Polarization
  • 8.6.2 Ferroelectric Relaxors with out-of-Plane Polarization
  • 8.6.3 Magnetoelastic Switching in a Magneto-Resistive Structure
  • 8.7 Conclusions
  • Acknowledgments
  • References
  • 9 Hybrid Spintronics-Strainronics
  • 9.1 Introduction
  • 9.1.1 Nanomagnetic Memory and Logic Devices: The Problem of Energy Dissipation in the Clocking Circuit
  • 9.1.2 Switching Nanomagnets with Strain Could Drastically Reduce Energy Dissipation: Hybrid Spintronics-Straintronics Overview
  • 9.1.3 Landau-Lifshitz-Gilbert (LLG) Equation
  • 9.2 Nanomagnetic Memory Switched with Strain
  • 9.2.1 Complete Magnetization Reversal (180° Switching): Complex out-of-Plane Dynamics
  • 9.2.2 Switching the Magnetization between Two Mutually Perpendicular Stable Orientations and Extension to Stable Orientations with Angular Separation >90°
  • 9.2.3 Complete 180° Switching with Stress Alone
  • 9.2.4 Mixed Mode Switching of Magnetization by 180°: Acoustically Assisted Spin Transfer Torque (STT) Switching for Nonvolatile Memory
  • 9.3 Straintronic Clocking of Nanomagnetic Logic
  • 9.3.1 Two-State Dipole Coupled Nanomagnetic Logic
  • 9.3.2 Four-state Multiferroic Nanomagnetic Logic (NML)
  • 9.3.3 Switching Error in Dipole Coupled Nanomagnetic Logic (NML)
  • 9.3.4 Straintronic Nanomagnetic Logic Devices (NML)
  • 9.4 Summary and Conclusions
  • References
  • 10 Unconventional Nanocomputing with Physical Wave Interference Functions*
  • 10.1 Overview
  • 10.2 Spin Waves Physical Layer for WIF Implementation
  • 10.2.1 Physical Fabric Components
  • 10.3 Elementary WIF Operators for Logic
  • 10.4 Binary WIF Logic Design
  • 10.4.1 Binary WIF Full Adder
  • 10.4.2 Parallel Counters
  • 10.4.3 Benchmarking Binary WIF Circuits vs. CMOS
  • 10.4.4 WIF Topology Exploration
  • 10.5 Multivalued WIF Logic Design
  • 10.5.1 Multivalued Operators and Implementation Using WIF
  • 10.5.2 Multivalued Arithmetic Circuit Example: Quaternary Full Adder
  • 10.5.3 Benchmarking of WIF Multivalued Circuits vs. Conventional CMOS
  • 10.5.4 Input/Output Logic for Data Conversion between Binary and Radix-r Domains
  • 10.6 Microprocessors with WIF: Opportunities and Challenges
  • 10.7 Summary and Future Work
  • References
  • Index
  • Supplemental Images
  • EULA

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