This book continues to be a Morgan Kaufmann bestseller. This is no doubt in part because of the widespread fame of two of the authors: Ivan Sutherland is the recipient of both the ACM Turning Award and the IEEE Von Neumann Medal. These awards are considered the most prestigious offered by each of these professional computing societies. Sutherland and Bob Sproull are Sun fellows (and Vice Presidents) and are highly acclaimed experts in the design of graphics hardware and software. This is a slim book and a fast read. Veteran as well as junior designers easily benefit from the way the authors think about circuit design. And as an IEEE Micro book reviewer put it, "...There's another reason to read this book... It's a wonderful example of how world-class engineers think about a problem".
Ivan E. Sutherland, a vice president and fellow at Sun Microsystems, received the Turing Award and the Von Neumann Medal for his pioneering contributions in the fields of computer graphics and microelectronic design. Robert F. Sproull is an internationally noted expert on the design of graphics hardware and software. He too is a vice president and fellow at Sun. David Money Harris is an associate professor of engineering at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Evans & Sutherland, and other design companies. David's passions include teaching, building chips, and exploring the outdoors. When he is not at work, he can usually be found hiking, mountaineering, or rock climbing. He particularly enjoys hiking with his son, Abraham, who was born at the start of this book project. David holds about a dozen patents and is the author of three other textbooks on chip design, as well as two guidebooks to the Southern California mountains.
1 The Method of Logical Effort 2 Design Examples 3 Deriving the Method of Logical Effort 4 Calculating the Logical Effort of Gates 5 Calibrating the Model 6 Asymmetric Logic Gates 7 Unequal Rising and Falling Delays 8 Circuit Families 9 Forks of Amplifiers 10 Branches and Interconnect 11 Wide Structures 12 Conclusions A Cast of Characters B Reference process parameters C Logical Effort Tools D Solutions
Dewey Decimal Classfication (DDC)