Skew-Tolerant Circuit Design

 
 
Morgan Kaufmann Publishers In
  • erschienen am 16. Juni 2000
 
  • Buch
  • |
  • Softcover
  • |
  • 300 Seiten
978-1-55860-636-4 (ISBN)
 

As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers.


This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues.
* Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial
* Provides incisive instruction and advice punctuated by humorous illustrations
* Includes exercises to test understanding of key concepts and solutions to selected exercises

New
  • Englisch
  • San Francisco
  • |
  • USA
Elsevier Science & Technology
  • Für Beruf und Forschung
  • |
  • Engineers designing high-speed microprocessors and DSPs as well as postgraduate students in advanced VLSI design courses
  • Höhe: 234 mm
  • |
  • Breite: 188 mm
  • |
  • Dicke: 18 mm
  • 494 gr
978-1-55860-636-4 (9781558606364)
155860636X (155860636X)
weitere Ausgaben werden ermittelt
David Money Harris is an associate professor of engineering at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Evans & Sutherland, and other design companies. David's passions include teaching, building chips, and exploring the outdoors. When he is not at work, he can usually be found hiking, mountaineering, or rock climbing. He particularly enjoys hiking with his son, Abraham, who was born at the start of this book project. David holds about a dozen patents and is the author of three other textbooks on chip design, as well as two guidebooks to the Southern California mountains.
Chapter 1 - Introduction Chapter 2 - Fundamental Concepts Chapter 3 - IP Switching Chapter 4 - Tag Switching Chapter 5 - MPLS Core Protocols Chapter 6 - Quality of Service Chapter 7 - Constraint--based routing Chapter 8 - Virtual Private Networks
"Harris leads the way to more performance with a clear strategy for design. He shows how to combine logic and latching to do more logic in less time. In an era where less stuff means higher speed, everyone interested in high performance logic must understand these techniques or be left behind." - Ivan Sutherland, Vice President and Fellow, Sun Microsystems "The author thoroughly explains important circuit design techniques including various types of latch design styles, clocking strategies, and methods of accounting for clock skew. That all of this is captured in one place is one of the great strengths of this book." - Emily J. Shriver, Alpha Development Group, Compaq Computer Corporation
Dewey Decimal Classfication (DDC)

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